Linked list, Bit manipulation, Pipeline
Senior Asic Design Engineer Interview Questions
1,319 senior asic design engineer interview questions shared by candidates
basic concept of pipeline state machine of sequence detector C program of a function about pattern replace
STA algorithms.
Phone interview Design gates using CMOS transistors. Build gates using 2-to-1 muxes. Write a verilog module that takes a clock signal and outputs another clock signal that is 3 times lower in frequency. The number of states required for a sequence recognizer.
gate level, digital circuit like counter, power problems
Explain previous projects worked o
1) Data structures and algorithms
Puzzles and a lot of RTL coding.
Design a Verilog module that generates the perfect squares of natural numbers starting from 4.
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