It's about a clock frequency problem, something related to time borrowing.
Senior Asic Design Engineer Interview Questions
1,319 senior asic design engineer interview questions shared by candidates
CDC and metastability and ways to implement synchronizer in circuit, also how to use asynchronous FIFO and the logic goes in building FIFO
How does clock divide by 2 work
Moderate, no unexpected questions asked.
A hard Verilog question for a system.
1. Basics of CMOS. 2. FIFO 3. Digital Electronics.
Read after write sequence implementation
One hot encoding, FSM divide by 3, Verilog coding.
They concentrate more on your technical knowledge over Architectural Design and Problems you tackle. As well as a Ciding for Automation
min and max timing violation
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