Given a diagram, how would you verify a design/check output data. Computer arch basics and design questions
Senior Asic Design Engineer Interview Questions
1,319 senior asic design engineer interview questions shared by candidates
functional, code coverage ,priority encoder explanation, SV
Calculate bandwidth for 16 bit data bus, data rate: 50 MHz and only 25% of time.
Why would we pick you?
1. Some simple random stimulus with specified constraints
related to RTL and UVM
Setup-Hold timing inter-relationship question, framed by way of max frequency of operation
Provided a waveform and asked to design a circuit for that.
I had a phone screen - basic SV and UVM multiple choice questions. Second round - OOPs concepts, some verification concepts (types of coverage, stimulus).
System verilog, UVM scoreboard/monitor coding
Viewing 1201 - 1210 interview questions