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Design Verification Interview Questions
3,723 design verification interview questions shared by candidates
Find a bug in Fifo verilog code
C++ Questions, memory allocation
Walk through the CV and deep dive the previous project technical details. Many general questions related to verification methodology.
Technical questions related to digital design, based on projects from your CV and verification languages, methodologies. Questions were basic ones and there were a few scenario based questions too.
asked in system verilog and UVM
Stack, heap, computer architecture related questions. Cache coherence.
Verification plan for a given scenario, what are the possible ways we can verify.
What is the difference between calloc and malloc?
They asked: blocking, nonblocking statement, asked to write a code for a given circuit, then they asked about asynchronous, synchronous reset, how and where they are applied. In second round, they asked question based on processor design, FIFO, STA.
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