A packet with address, and data. The address range is split into 4 regions. Create a class that will generate 100 packets and cover all possible ranges.
Design Verification Interview Questions
3,723 design verification interview questions shared by candidates
Given 3 blocks, asked to make signal connections among them and what is my approach to verify
they ask me my preference of work
What I know about verilog
develop exor gate using 2:1 mux and draw the circuit
What are some ways for error testing/handling in software?
What conflict is possible when you have a weak memory model and another memory location containing flags that indicate the status of another memory location (described above)
Technical questions related to job role
They shared the specific scenario and asked how would I solve it. So they are checking your problem-solving skills.
What motivates me from day to day
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