tlm and its benefits. difference between blocking and nonblocking transactions
Design Verification Interview Questions
3,715 design verification interview questions shared by candidates
- about SV, FIFO design, arbiter design
MESI Protocol FIFO Verilog and condition for full and empty Build FSM for 20 story building elevator (you have control in elevator and controls on every floor and discuss what floors take priority Build a clock divider to take 2MHz signal to 1MHz Build a 4:1 MUX using behavioral verilog than structural verilog Tell me how many bits per tag, offset, and addr based on cache structure (1MB 8 way associative) Tell me 5 stage pipeline Tell me about different hazards and explain types of data hazards how would you go beyond 5 stage pipeline
Draw a state machine that accepts the sequence 101
Strong focus on making sure Veriff and the candidate are on the same page in terms of values, future goals etc. (for example - relation to Veriff's mission)
To assemble mux 4x1 with mux 2x1
How can you swap two numbers without using an extra temporary variable? Note that each variable is limited by a certain number of bytes
do I know objective-oriented coding
Why do you want to join Hologic?
Asked lots of questions about Cache and Virtual Memory, including Cache set, index, associativity, etc. CPU superscalar, Out of Order, etc. Address translation, aliasing problem
Viewing 3701 - 3710 interview questions