Memory - 4byte accessible --- constraint randomize and select one random memory address
Design Verification Engineer Interview Questions
3,715 design verification engineer interview questions shared by candidates
Describe the handshake between UVM agent and UVM sequencer
Explain gray code and FIFO techinique?
What do you do to relieve stress?
How to do numerous tasks and kill off 1 task if any finish. Then wait for all to finish.
Teamwork experience (get things back on track)
How to deal with difficult customers
implement 4*1 mux using ternary operator
First interview was totally dedicated to the projects I had mentioned in my resume.
it was a set of basics
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