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Design Verification Engineer Interview Questions
3,720 design verification engineer interview questions shared by candidates
Tell me your personal advantages and disadvantages.
Tell about yourself, experience of previous employment and certifications ?
Unexpected question was string manipulation using C++. Since I have not used C++ for strings since I have started working and it is not a hands-on question that has anything to do with the technical expertise of the person, it was kind of unexpected.
SystemVerilog basics and UVM basics
Why are you interested in working with Intria?
1. Explain your minor project. 2. They focused on Digital Electronics and Verilog coding skills 3. Aptitude questions 4. Some computer architecture questions
Why are you choosing VLSI?
dld, verilog, sv, uvm, protocols
None. Read a script.
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