If you had to choose between two vacuums, same price, what would be some of the things you would consider?
Design Verification Engineer Interview Questions
3,722 design verification engineer interview questions shared by candidates
Questions on writing constraints for the given sequence.
class A; function int foo(); int a; return ++a; endfunction endclass program tb; A a; int b, c; initial begin for(int i = 0; i < 10; i++) begin b = a.foo(); c = foo(); $display("B = %0d", b); $display("C = %0d", c); end end function int foo(); int a; return ++a; endfunction
design question - design a system to identify if input bitstream is divisible by 5 - taking a 16bit stream, programming - print matrix spiral, etc. Also assertion questions, UVM
First interview - I was asked to write pseudo code for memory allocation (like malloc/free). Second interview - I was asked to describe verification environment for a FIFO, considering sync/async. And to write a UVM monitor.
Tell me a bit about yourself.
Immediate vs. Concurrent Assertions .
What is a pipeline driver?
I shared my experience in the projects that I worked on so far.
Edge trigger variation coding in RTL
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