what is your verification process?
Design Verification Engineer Interview Questions
3,722 design verification engineer interview questions shared by candidates
digital design
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Typical behavioral questions
Interviewer jeopardises most of the time,never get distracted, be confident on your answer
At first, they ask me about my previous experience and started to ask question about it. Then it became technical. Some question about gain, impedance, noise, bandwidth, transient response (under switching events) in common circuit topologies. What strategy would I use to face PVT variations on a circuit. Definition of Phase noise and Jitter and some questions about the advantages of flash architecture in ADC.
Fsm, divide by 5 counter, verilog
Explain the UVM Sequencer driver communication
logic gates rc network cmos basics operation regions vi characteristics diodes fet
Tell me about a time when you created a product for a company that made your job easier; what was it and how did it work?
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