1. C code- swap by reference 2. Perl basics 3. cache coherency, cache mapping, memory repair, power domain crossing - use of isolation cells. 4. Memory organization 5. Pipeline hazards -> WAW, RAW etc.. register renaming, pipeline forwarding etc 6. Clock domain crossing - how do you handle it? which clk to be fed to synchronizer, lock up latch etc 7. MBIST verification - The interviewer was mad, he kept on asking questions on mbist despite me telling I have not worked on MBIST. I gave up and blabbered something. He kept on asking pin-pointed questions for NCG hire, who usually knows bigger picture of MBIST. He asked how many cycles to verify 8 bit pattern, is it verified at speed? I did not know that 8. JTAG 1500 - I have never worked on 1500, he asked for pins I told WSI, WSO etc.. He asked for JTAG ports instead of signals!! I got confused and blabbed something instead of telling I dont know (my bad!). He actually meant JTAG signals like update, capture, shift!! 9. CLK domain crossing : He asked about synchronizer cells and how they prevent metastability, I gave generic answer, he wanted textbook answer. Why sync cells are used instead of two f/f's connected together! I dont know man, I did not work on it!
Cpu Design Engineer Interview Questions
222 cpu design engineer interview questions shared by candidates
Have you had experience in CPU physical layout design?
Impact of changing branch outcome stage detection in performance?
About my cv. Mainly about compiler, OS, and projects I've done.
Why are you interested in this internship?
Coding assignment in Python + some C questions
5 stages on Piplelined CPU
i have mentioned all the interview question above
How would you verify a RAM memory with a single port read/write?
Verification methodology, computer architecture, data structures and algorithms, digital logic, Verilog
Viewing 31 - 40 interview questions