32Kb cache, 2 way assoc. and 64B line. what is the cache state and line state according to MESI when. Read 0x010F30 then write 0x880F00 then write 0x010F20
Cpu Design Engineer Interview Questions
222 cpu design engineer interview questions shared by candidates
I was asked in an interview a code question about the correctness of a string in terms of brackets of all kinds)}]. In addition, I was asked a question about how to implement "malloc" and "free" in C.
On-campus: Verilog code writing, simple hardware design question using muxes and counter that was approached from different levels of abstraction. Phone Interview: Entirely computer architecture questions, including cache coherency protocols, cache organizations
Virtual memory and paging, details of reservation stations, load store ordering, cache org, role of design verif and how do you interact with them.
What is one time where you had experienced a stressful situation and how did you handle it?
Explain how an out-of-order processor works? How do you implement register renaming? Difference between an architectural and physical register file
Q: Register renaming. How it works
What year are you in university, and what are you doing?
Out of order processor, importance ILP (and it's advantages), Digital design (realizing basic gates with a MUX)
How do you think you will fit in?
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