Asic Engineer Interview Questions

1,319 asic engineer interview questions shared by candidates

Technical Questions: Questions about Latch vs Flip-Flop. Draw a D-flip-Flop, linked them together to make a linear feedback shift register. Draw timing diagram. (Setup/Hold time). Draw complementary style inventor. (Pmos,Nmos). Why Pmos is on the top? talked about low power design principle. Problem solving: A problem about "Three boxes are labeled “Apples,” “Oranges,” and “Apples and Oranges.”". Google it. Write a program to find a parenthesis in a string. Ex: A(+SDF09)(u&(.
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Digital ASIC Design Graduate

Interviewed at Imagination Technologies

2.9
Mar 29, 2016

Technical Questions: Questions about Latch vs Flip-Flop. Draw a D-flip-Flop, linked them together to make a linear feedback shift register. Draw timing diagram. (Setup/Hold time). Draw complementary style inventor. (Pmos,Nmos). Why Pmos is on the top? talked about low power design principle. Problem solving: A problem about "Three boxes are labeled “Apples,” “Oranges,” and “Apples and Oranges.”". Google it. Write a program to find a parenthesis in a string. Ex: A(+SDF09)(u&(.

Round 3 1- Add 7 bits using 4 Full Adders 2- two Pipelines runnign parallely. 128 Bit register file. 4 read ports n 2 write ports. Convert it into 4 reg files with one read n one write ports for all. Find adv and dis adv. 3- Design a divide by 3 FSM checker
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ASIC Intern

Interviewed at NVIDIA

4.4
Apr 24, 2012

Round 3 1- Add 7 bits using 4 Full Adders 2- two Pipelines runnign parallely. 128 Bit register file. 4 read ports n 2 write ports. Convert it into 4 reg files with one read n one write ports for all. Find adv and dis adv. 3- Design a divide by 3 FSM checker

How do you as a back-end designer work with front-end (RTL/Synthesis) designers to solve tough timing problems, for example, under what circumstances do you absolutely need them to solve on their side? What information or files do you provide to them?
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ASIC Design Engineer

Interviewed at NVIDIA

4.4
May 14, 2019

How do you as a back-end designer work with front-end (RTL/Synthesis) designers to solve tough timing problems, for example, under what circumstances do you absolutely need them to solve on their side? What information or files do you provide to them?

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