1. Some simple random stimulus with specified constraints
Asic Engineer Interview Questions
1,319 asic engineer interview questions shared by candidates
Optimize a digital circuit for power and for delay, difference between a shift register and a FIFO, priotity MUXing, logic question
What will gm change if we enlarge the W/L of a transistor by 2. Compare the gm of a BJT and MOS device. Slew rate problem
Cache
Retiming for a 5 input OR
FIFO Design
Sequence detecting FSM, coding it in Verilog
Design Questions and some logic questions
Logical design, physical design, perl, System verilog (UVM)
Questions in digital design, timing violations, metastability
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