My previous experience, as well as a few mock examples related to verification and what my process would be
Asic Design Verification Engineer Interview Questions
273 asic design verification engineer interview questions shared by candidates
I don't remember the question clearly but something that had to do with implementing some methods in a (UVM-like) Scoreboard class.
Node insertion in linked list. Fibonacci series function, hardware to generate Fibonacci series, prime number generation hardware , STA concepts, clock domain crossing, use of synchronizes, skew and setup hold time violation.
Explain past work experience and Project details.
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
All questions were related to my previous experience, testing methodology, and problem solving skills. They also asked some basic oo concepts
what do u know about virtual pages
pass by value, pass by ref, function in c for fibonacci, pattern detector fsm, pipeline hazard
Constraint randomization based question linking to AXI and memory filling
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
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