Regarding testbench in sv and uvm
Asic Design Verification Engineer Interview Questions
274 asic design verification engineer interview questions shared by candidates
I was asked to give a brief on PCIe protocol
How does a JTAG probe work
Array, system verilog,uvm, mailbox Queue fifo configdb etc
basic knowledge about vlsi
Question on C programming * what is the difference between call by value and call by reference? Questions related to electronics? * combinational circuits * Sequential circuits *Implement 16:1 MUX using 4:1 mux *Explain S-R fliflop . * Differentiate between == and ===
What is the one thing that you are proud of yourself during the learning process ?
Domande legate a quali strategie usare per testare funzionalità di ASIC
A block diagram of a protocol block was given and was asked to write a SystemVerilog transactor code.
Basic questions about UVM
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