Clock domain crossings and reset domain crossings
Asic Design Engineer Interview Questions
1,319 asic design engineer interview questions shared by candidates
What is setup time and hold time? How would you fix these violations pre-silicon and post-silicon? What is the difference between clock skew, clock jitter, and clock uncertainty? Draw CMOS for a 1-input NOT gate, 2-input NOR gate, and 4-input NAND gate. Draw the circuit for a full-adder with minimal number of gates.
Memory controller design
Know the details of your past work experience.
1. Circuit Design 2. Physical Design 3. Scripting
what the keyword volatile means in C
What is your Best Accomplishment? What would you do under x condition? DRC v. LVS
All kinds of fork joins
Basic Digital Circuit and Analog Circuit Questions
Abstarct class vs Interface, inheritance,polymorphism…..etc Observer and Factory DP in details. Log file output analysis. Behavioural questions. Giving basic and simple designs with some specifications and elaborate a strategy to verify it.
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