How would you build a 4 to 1 mux with only 2 to 1 mux modules?
Asic Design Engineer Interview Questions
1,319 asic design engineer interview questions shared by candidates
How would you build a sequential block and combinational block in verilog? what will you use "always@ * "?
7. Dual port RAM operation (if read and write req to the same location at a time?)
6. STA concepts
Basic Digital Electronics and CMOS fundamentals
Q: Code for algorithm to sort an array of signed integers (can't use any built in language support for sorting).
Q: Code a Verilog snippet for clock with duty cycle != 50%.
ASIC and PNR flow
Basic questions on Digital electronics and C programming.
traffic light controller question based out of counter
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