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Asic Design Engineer Interview Questions
1,319 asic design engineer interview questions shared by candidates
cross clock domain questions
asynchronous clock domain crossing, FIFO pointer logic, timing constraints, a divide by 3 clock generator
How to build a fsm sequence detector
Where do you see yourself in 5-10 years?
Some cutting square questions,
Problem on timing analysis
What is aliasing, and how can you make sure you aren't reading an aliased signal of unknown frequency on an oscope?
Decimal to gray function with logic gates
Be strong in your basics
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