They asked a lot questions on pipeline design. Like how to optimize the overall ipc regarding branch? Is it possible to get branch resolved in decode stage?
Asic Design Engineer Interview Questions
1,318 asic design engineer interview questions shared by candidates
nothing in particular
round robin algorithm, scheduling? state diagram?
Black box CRC circuit checking...
clock divider / mealy vs moor fsm / through my resume project / setup time hold time
Pipeline stuff
Garage door opener in verilog
1) FIFO RTL design 2) how to optimize power 3) steps to take ECO
virtual memory standard libraries in C how to build a cache how will you move data in cache what is recursion linked lists, binary tree, flat architecture, how a CPU would work
virtual memory standard libraries in C how to build a cache how will you move data in cache what is recursion linked lists, binary tree, flat architecture, how a CPU would work
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