Q: Explained 2-stage pipelined adder
Asic Design Engineer Interview Questions
1,319 asic design engineer interview questions shared by candidates
Asked about timing analysis
Difference between Moore state machine and Mealy state machine.
Tested for knowledge of position applied to.
Why I want to join
As an ASIC verification Engineer Most of the questions were based on system Verilog and UVM. 1: Components of UVM, which components have you worked. 2: Phases in UVM 3: Assertions
sorting, patterns ,microcontrollers, swaping, encapsulation
what project you have done
FIFO fills at a particular rate "x" and drains at rate "y". How deep does it need to be to sustain 100% throughput.
The questions were basically related to digital electronics ,puzzle,aptitude.
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