Questions on logic design, synthesis and computer architecture, such as cross clock domain issues, cache, state machine, low-power design techniques. Only one behavioural question. Also asked about past projects.
Asic Design Engineer Interview Questions
1,319 asic design engineer interview questions shared by candidates
Basic design and verification questions.
describe how axi transaction works, valid ready
Compare the analog and digital PLL, pros and cons
Basics on ddr verification and functional coverage
Q: Basics of system verilog classes, creating parent class object using child class handle, $cast concept. Fork-join processes, how is control handed to code outside the fork in the 3 cases; code a watch-dog timer to time out if an event does not occur by the end of certain transaction.
Wat is er al eens fout gelopen in eerdere projecten?
Theory questions on Rcmin rcmax v min vmax cmos spef cts
Digital electronics, Perl, Verification flow
Flip Flop T setup T hold
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