Write constraints for unique elements in an array. Write assertions for different scenarios of AXI protocol. Basics of UVM including testbench components, phases, TLM ports.
Asic Design Engineer Interview Questions
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Questions on protocols like API, AXI, AHB, API, UART.
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AMBA AXI, AHB, APB related and Interconnect related questions.
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* job experience and roles * how do u verify a scheduler * A block has inputs of network pkts and buffers/pipelines them through an RTL. RTL has counters which will tell how many packets are sent. How to verify? (Counters Read => count. Write => clear) How to verify counts? what cases will u test? * Given a sys verilog code for a memory model and asked to implement read/write/move functions and write checks
Systemverilog and UVM questions
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