Asygn is based in Grenoble (French Alps), designing high performance electronics for sensors and RF applications. With a team of 40 people, Asygn’s activity is backed by a high level of expertise and in-depth knowledge of high-resolution sensor interface, ultra-low power and RF design.
Our team design RF and millimeter wave products for Satellite, Automotive and consumer telecommunications applications. Our expertise is in the design of analog, RF and mmW systems up to 100 GHz including IC design, package integration, antenna design, architecture and system design. We’re working with the leading companies in those domains for more than 10 years, we’ve recently delivered analog beamforming circuits for SATCOM or MIMO transceiver IC for telecommunications, for instance.
As we are starting a new RF/mmW product family, we are hiring an RFIC designer.

Job description

What we’re looking for is a creative designer with a solid experience in RF/mmW IC design (RX, TX, LO), modeling, verification of actives and passive blocks on CMOS and BiCMOS sub-µm technology process.
As a RFIC design engineer, you’ll mainly focus on :

• Block topology definition based on experience, state of the art, and product requirement
• Design (schematic, layout) and verif (RF/DC/… simulation, DRC, LVS, …) of core circuit blocks and associated functions (bias, supply, DFT, …)
• Top design (assembly of core blocks), integrations of analog and digital blocks, top performance verification and circuit sign-off validation
• Build deliverables (technical reports, design databases)
• Characterize circuits in the lab

Profile

Education and Experience Requirements:
Ph.D. or M.S in Electrical Engineering with experience in RF IC development.
Additional Qualifications:

• Strong skills in RF/mmW design at system and transistor level. Experience with LNA, PA, LO and/or Mixer at millimeter wave frequencies.
• Electromagnetic simulation experience for integrated passive design and package coupling extraction.
• Strong intuitive and analytical understanding of transistor level design, layout, and simulation.
• Experience with Cadence, Mentor Graphics and Keysight tools
• Knowledge and experience with experimental/debug verification in the lab
• Eager for field returns and continuous improvement
• Proficient in written and spoken English. French language highly appreciated.