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NXP CAEN is seeking a Senior DfT Engineer to contribute to the design and implementation of Design-for-Test (DFT) solutions for complex System-on-Chip (SoC) products for Automotive Market, ensuring high test coverage and efficient manufacturing test flows.
Your Responsibilities:
Develop and implement DFT architectures and methodologies for digital and mixed-signal IPs and SoCs, including scan, JTAG, memory BIST, and logic BIST.
Perform DFT insertion and verification using industry-standard EDA tools.
Generate test patterns (e.g., ATPG, BIST patterns) and ensure their effectiveness in achieving target fault coverage.
Analyze test coverage reports and work with design teams to identify and resolve DFT-related design issues.
Collaborate with verification and test engineering teams to define and validate manufacturing test plans.
Debug silicon test failures and provide support for production ramp-up.
Contribute to the continuous improvement of DFT methodologies and flows.
Document DFT specifications, implementation details, and test plans.
Your Profile:
Master's degree in Electrical Engineering,
Proven experience (7+ years) in DFT design and verification for complex SoCs.
Strong understanding of various DFT techniques (Scan, JTAG, MBIST, LBIST, Boundary Scan).
Proficiency with industry-standard EDA tools for DFT insertion, ATPG, and fault simulation (e.g., Tessent, Synopsys DFT Compiler, Cadence Modus, Synopsys Z01X).
Solid understanding of digital design principles and ASIC/SoC design flow.
Experience with Security and Safety is a plus.
Experience with scripting languages (e.g., Tcl, Python, Perl) for automation.
Familiarity with semiconductor manufacturing test processes is a plus.
Excellent problem-solving, analytical, and communication skills.
Ability to work effectively in a collaborative team environment.