Whatever you have worked on, Specialisation ,SV and UVM. Prepare well whatever you have mentioned in your resume.
Verification Engineer Interview Questions
3,715 verification engineer interview questions shared by candidates
Digital Electronics:- FSM, Register, Flip flop, MUX. Verilog:- write program for FSM, clock generator, mux. SystemVerilog:- programming question based on randomisation. UVM:- write code for driver sequencer ,Tlm ports.
Basics and some basic circuit verification
Tell me about yourself?
explain ASIC flow
already sv is there.... why UVM required??
explain about UVM TB architecture? explain what is UVM factory
What is your weakest quality?
How will you initiate a verification?
General discussion on my coding background and course work
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