program for ring counter and Johnson counter in verilog
Asic Design Verification Engineer Interview Questions
274 asic design verification engineer interview questions shared by candidates
program for pattern detector for FSM
write code for generating clock of 50MHz frequency, with 5% jitter and duty cycle.
what rating you will give to yourshelf?
1. Build a circuit to ti produce a signal high whenever output changes also asked this to be implemented in terms of FSM suitable for RTL CODING. Asked about data dependencies and control dependencies, caches types and cache replacement policies. What is virtual fiction in c++ and recursive functions code in c Mostly basics
basic resume, metastability, race condition, how classes are destroyed in SV?, basic object oriented concepts.
Q: Number of test vectors for a priority encoder with "n" inputs.
Q: FSM for detecting a particular sequence.
From where did I completed my education
Uvm, system verilog
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