Clock pulse generator STA concepts
Asic Design Verification Engineer Interview Questions
274 asic design verification engineer interview questions shared by candidates
how to use UVM events and UVM pool
Basic pipelining, C/C++ and Perl coding, Verilog, FSMs, Caches
FSM pattern detector, C++ code for fibonacci sequence, swap function, linux based question to replace all instances of a word in a file with another word without opening the file, blocking/non blocking operators in verilog.
describe what is virtual function. and difference between that and pure virtual function?
Phone interview questions: 1. How do you achieve run time polymorphism? 2. What is meant by casting of objects?
Knowledge about verification environments
Explain the UVM Sequencer driver communication
Digital questions, UVM environment based questions
coding questions consists of - creating sequences - creating constraints for a given problem - creating an algo for data query
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