How do you reduce time complexity from O(n) to O(log2n) (for above subroutine)?
Asic Design Engineer Interview Questions
1,319 asic design engineer interview questions shared by candidates
Draw a FSM sequence detector
Explain previous projects worked o
CDC and metastability and ways to implement synchronizer in circuit, also how to use asynchronous FIFO and the logic goes in building FIFO
1. Basics of CMOS. 2. FIFO 3. Digital Electronics.
Computer Architecture, FIFO depth calculation, how to design Power, Performance, or Area-efficient RTLs, also some questions regarding pipeline hazards.
Describe how you solved a problem on a project
Questions from OA will be asked
basic concept of pipeline state machine of sequence detector C program of a function about pattern replace
STA algorithms.
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